The present application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2002-140077 filed on May 15, 2002, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices, and particularly relates to a nonvolatile semiconductor memory device having a virtual-ground memory array.
2. Description of the Related Art
In the virtual-ground memory array, bit lines are formed of diffusion layers. Among the diffusion layers corresponding to a pair of bit lines, the one that is coupled to the ground potential functions as a source, and the other that is coupled to the power supply potential serves as a drain. In such a virtual-ground memory array, the bit-line diffusion layers of a memory cell are shared by adjacent memory cells that are situated alongside in the direction of word-line extension. Because of this, the drain contact that is normally provided for each memory cell in the NOR-type memory cell array is not necessary, thereby achieving size reduction of memory cells.
FIG. 1 is a circuit diagram showing a portion of a virtual-ground memory array.
The virtual-ground memory array of FIG. 1 includes memory cells M00 through M23, bit lines BL0 through BL4, and word lines WL0 through WL2. When data is to be read from the memory cell M02, the word line WL0 is set to a predetermined potential to select all the memory cells connected to the word line WL. Further, the bit lines BL0 through BL2 are set to a drain potential of 1V, for example, and the bit lines BL3 and BL4 are coupled to the ground potential. With these settings, the bit line BL2 serves as a drain, and the bit line BL3 functions as a source with respect to the memory cell M02. As shown in FIG. 1, an electric current Im02 flowing through the memory cell M02 is equal to an electric current Ibl2 running through the bit line BL2. The data of the memory cell M02 is detected by sensing the electric current Ibl2 by use of a sense amplifier (not shown).
In such read operation, the reason why the bit line BL1 is set to 1V to equalize the bit lines BL1 and BL2 is that there is a need to prevent a leak current from running from the bit line BL2 to the bit line BL1 through the memory cell M01. Under the presence of such a leak current, the electric current Im02 running through the memory cell M02 would be different from the electric current Ibl2 flowing through the bit line BL2, so that the detection of the current Ibl2 may not result in the correct data of the memory cell being obtained.
In the configuration that prevents a leak current as described above, the potential that is applied to the adjacent bit line BL1 is referred to as a precharge potential, and the potential that is applied to the read bit line BL2 is referred to as a sense potential.
Since the bit lines of a virtual-ground memory array are formed of impurity diffusion layers, the resistance of the bit lines is relatively large, compared to the NOR-type nonvolatile memories in which bit lines are provided as hardwires formed of a low-resistance metal. A potential drop is thus likely to occur along the bit lines. As a result, the sense potential and the precharge potential may not be set to the same voltage as desired.
A typical construction is such that the sense potential and the precharge potential are supplied from separate circuits, which may result in the supply timing being different between the sense potential and the precharge potential. In such a case, the sense potential and the precharge potential may not exhibit the same voltage level.
When the data of the memory cell M02 shown in FIG. 1 is to be detected, almost no leak current flows through the memory cell M01 if the threshold potential of the adjacent memory cell M01 is high due to the data status of xe2x80x9c0xe2x80x9d of the memory cell M01. This is the case even when there is a difference between the precharge potential and the sense potential. If the threshold potential of the memory cell M01 is low due to the data status of xe2x80x9c1xe2x80x9d thereof, however, a difference between the precharge potential and the sense potential will affect the read operation.
Further, it is possible that the threshold of a memory cell may be erroneously sensed due to the effect of a leak current during program-verify operations or erase-verify operations. In such a case, the reliability of verify operations may suffer greatly. This results in the threshold potential of data xe2x80x9c0xe2x80x9d and data xe2x80x9c1xe2x80x9d having increased variation between different memory cells, which reduces a margin for threshold fluctuation caused by a thermally induced stress or the like. As a result, the reliability of the nonvolatile memory is lowered.
Accordingly, there is a need for a nonvolatile semiconductor memory device which allows data to be correctly sensed even if a leak current exists in the virtual-ground memory array.
It is a general object of the present invention to provide a nonvolatile semiconductor memory device that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a nonvolatile semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a nonvolatile semiconductor memory device, including a virtual-ground memory array which includes a plurality of word lines and a plurality of bit lines, a row decoder which selectively activates one of the word lines, a column decoder which applies a sense potential to one of the bit lines, and couples all the remaining ones of the bit lines to a ground potential, and a sense amplifier which compares an electric current running through the one of the bit lines with a first reference current and a second reference current so as to sense a data state of two memory cells that are connected to the one of the word lines and share the one of the bit lines, the sensed data state including a first state in which both of the two memory cells are xe2x80x9c0xe2x80x9d, a second state in which both of the two memory cells are xe2x80x9c1xe2x80x9d, and a third state in which one of the two memory cells is xe2x80x9c1xe2x80x9d and another of the two memory cells is xe2x80x9c0xe2x80x9d.
In the nonvolatile semiconductor memory device as described above, a memory cell that acts as a current leaking path in the conventional art is included as an object of data sensing, so that the two memory cells sharing the sensed bit line are both treated as objects of data sensing. The electric current flowing through this bit line is compared with the two different reference currents, thereby sensing the lump-sum data state of the two memory cells. Since all the bit lines other than the sensed bit line are coupled to the ground potential at the time of data sensing, a precharge operation of bit lines that are necessary in the conventional art is no longer required. Further, the ground potential is extremely stable in comparison with the precharge potential, and is not susceptible to a potential drop caused by bit-line resistance. Accordingly, the present invention can completely eliminate erroneous reading of data that occurs in the conventional art due to an unstable potential difference between the sensed bit line and the precharged bit lines.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.